The present invention relates to a memory circuit and to a method of replacing a column of a memory array.
It is known to make memory circuits tolerant of defects, for example, by providing spare memory locations for substitution into the memory array for any defective locations. For example, GB-A-1550 675 describes a system in which individual cells of a spare memory row or column can be substituted for defective cells of a memory array. In this system, the address of each defective cell is stored such that when it is required to address that defective cell, a replacement cell is addressed in its stead. GB-A-1398438 and 1455716 also describe systems where replacement locations are addressed instead of locations known to be defective. However, in GB-A-1398438 a defective row of the array is replaced by a spare row whilst in GB-A-1455716 a defective sector is replaced by a spare sector.
In addition, an EPROM with a nine block cell array which can be used as an 8 bit memory with the ninth block providing a redundant block is described in "A 288K CMOS EPROM with redundancy" by M. Yoshida et al, pages 544-549 of IEEE Journal of Solid-State Circuits, Vol SC-18, No. 5, October 1983.
Until recently, microprocessors in particular have operated using relatively small data words, for example, of 8 bits or less and the memory arrays therefore have been kept quite narrow. As the width, that is the number of columns, of a memory array is increased, it becomes more difficult to provide for access to the array such that each location can be accessed in substantially the same time and such that each location "looks" substantially the same to the processor. Because of this, any redundancy has previously been provided as spare rows to replace rows of the array.